Reducing the size of electronic devices presents various technical challenges. As computer chips become smaller, techniques for mounting those chips to circuit boards become increasingly complex. One technique that is often used for mounting chips to circuit boards is referred to as ball grid array, wherein solder balls are disposed on electrical contacts at the bottom of the chip. The solder balls are soldered to corresponding contact pads on the circuit board. The circuit board's contact pads may be electrically coupled to conductive through holes, referred to as vias, that provide routing of signals from the chip to other components mounted to the circuit board. Chips such as Application Specific Integrated circuits (ASICs) often include power and ground connections to the circuit board. Capacitors, often referred to as “bypass capacitors” or “decoupling capacitors,” are usually coupled across the power and ground connections to filter out unwanted electrical noise that may be generated by the power supply. The bypass capacitors may be disposed on the bottom side of the circuit board within the footprint of the ASIC.
As chips such as ASICs grow in complexity, and shrink in size, the ball pitch grid pattern also shrinks. As the ball pitch grid patterns become smaller, less room is available on the circuit board for components such as bypass capacitors. One technique that has been developed to overcome this challenge is referred to as “Via in Pad,” which enables the bypass capacitors to be disposed directly under the via, in other words, covering the via on the bottom side of the circuit board. However, the Via in Pad technique adds additional cost to the process of fabricating the circuit board. For example, Via in Pad typically use a via filling and plating process, referred to as Plated Over Filled Via (POFV), which introduces significant manufacturing cost for each circuit board.